1. Field of the Invention
The present invention relates generally to thin film transistors (TFT) and methods of evaluating reliability thereof, and more specifically, to a TFT including a channel layer of a silicon thin film and a gate insulating film of a silicon oxide film, and a method of evaluating reliability thereof.
2. Description of the Background Art
TFTs are used for load transistors in the memory cells of a static random access memory (SRAM) or driver transistors for liquid crystal television pixels. When such products incorporated with TFTs are marketed, the reliability of TFTs should be evaluated.
In FIG. 22, a typical top gate type P channel TFT is illustrated in a schematic cross section. In the TFT, an insulating film 2a is formed on a substrate 1. A polysilicon film 3 is formed on insulating film 2a. Polysilicon film 3 may be replaced with a monocrystalline silicon film or an amorphous silicon film. Source/drain regions 4 and a channel region 5 are included in polysilicon layer 3. A gate electrode 7 is formed on polysilicon layer 3 with a gate insulating film 6 of a silicon oxide film therebetween. Polysilicon layer 3 and gate electrode 7 are covered with a silicon oxide film 2b. An aluminum interconnection 8 is connected to each of source/drain regions 4 through a contact hole provided in silicon oxide film 2b. More specifically, the TFT in FIG. 22 is an MOS (Metal Oxide Semiconductor) type FET (Field Effect Transistor) with polysilicon layer 3 serving as an active region.
For reliability evaluation tests for the TFT as illustrated in FIG. 22, a hot carrier stress test, a breakdown voltage test for gate insulating film 6 or the like have been conducted.
FIG. 23 sets forth one example of a bias condition in such a hot carrier stress test. In this example, source voltage V.sub.S applied to source S is 0V, gate voltage V.sub.G applied to gate G is -7V, drain voltage V.sub.D applied to drain D is -7V, and current continues to be passed between source S and drain D for a long period of time. It has been established that if polysilicon film 3 is sufficiently hydrogenated, the electrical characteristic of the TFT hardly changes before and after such a hot carrier stress test (see International Reliability Physics Society Proceedings, 1992, pp. 63-67).
In FIG. 24, one example of a breakdown voltage evaluation test for a gate insulating film in a TFT is illustrated. In this example, for V.sub.S =V.sub.D =0V, gate voltage V.sub.G is gradually changed from 0V toward negative voltage. At the time, the gate voltage V.sub.G at which gate insulating film 6 is broken down is called gate breakdown voltage. When a silicon oxide film as thick as 250 .ANG. is used for a gate insulating film, the gate breakdown voltage is about 25V. For a power supply voltage of 5V, a gate breakdown voltage of 25V would be enough. The insulation breakdown voltage of a silicon oxide film is generally about 10 MV/cm expressed in electric field, and a breakdown voltage for a gate insulating film having an arbitrary thickness can be estimated from the value of the electric field.
It has been known that in a bulk silicon monocrystalline MOSFET the characteristic of the bulk MOSFET slightly degrades by a -BT (negative bias temperature) stress test by which the gate is supplied with constant voltage V.sub.G and maintained at an elevated constant temperature T.
The influence of -BT stress however is not exactly known. TFTs are therefore incorporated in SRAMs and the like and marketed without reliability evaluation by -BT stress tests.